In the field of signal processing devices, such as microcontrollers, and in particular in relation to such devices targeted at low power applications, it is known for such devices to support multiple power modes. Within each power mode, different features of the device may be operational, for example, some features may be clock-gated or power-gated depending on the particular power mode. Irrespective of the power mode in operation, a user wants to receive the best performance available. In particular, achieving the best performance with the lowest clock frequency is a key objective; if the device has to be clocked for longer or faster to accommodate poor performance, then this directly impacts the total power consumption, which in low power applications is unacceptable.
The optimal device configuration from a performance perspective in one power mode is not necessarily the optimal configuration in another power mode. In particular, the optimization of data paths between, for example, central processing unit (CPU) cores and memory elements, requires an in-depth understanding of the underlying system to correctly configure, and which can be significantly affected by changes in power mode.
Microcontroller devices and the like typically comprise various configurable elements that control the data paths between CPU cores and memory elements, such as a system crossbar, flash memory controller with associated pre-fetch buffering schemes, etc. Typically, such elements are configured by customers based on the individual requirements etc. of their particular applications.
However, due to difficulty for customers to gain an in-depth understanding of the underlying system and the complexities involved in re-configuring such elements within a typical microcontroller device, such devices are often configured in a non-optimized manner for one or more power modes.